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74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs
January 1995 Revised January 1999
74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs
General Description
The ABT16501 18-bit universal bus transceiver combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CLKAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A bus data is stored in the latch/flip-flop on the LOW-to-HIGH transition of CLKAB. Output-enable OEAB is active-high. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state. Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are complementary (OEAB is active HIGH and OEBA is active LOW). To ensure the high-impedance state during power up or power down, OE inputs should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
Features
s Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode s Flow-through architecture optimizes PCB layout s Guaranteed latch-up protection s High impedance glitch free bus loading during entire power up and power down cycle s Non-destructive hot insertion capability
Ordering Code:
Order Number 74ABT16501CSSC 74ABT16501CMTD Package Number MS56A MTD56 Package Description 56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape or Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
Pin Assignment for SSOP
Function Table
OEAB L H H H H H H LEAB X H H L L L L
(Note 1) Output A X L H L H X X B Z L H L H B0 (Note 2) B0 (Note 3) X X X H L
Inputs CLKAB
Note 1: A-to-B data flow is shown: B-to-A flow is similar but uses OEBA, LEBA, and CLKBA. Note 2: Output level before the indicated steady-state input conditions were established. Note 3: Output level before the indicated steady-state input conditions were established, provided that CLKAB was HIGH before LEAB went LOW.
(c) 1999 Fairchild Semiconductor Corporation
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74ABT16501
Logic Diagram
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74ABT16501
Absolute Maximum Ratings(Note 4)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 5) Input Current (Note 5) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -0.5V to 5.5V -0.5V to VCC -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA -65C to +150C -55C to +125C -55C to +150C
DC Latchup Source Current Over Voltage Latchup (I/O)
-500 mA 10V
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage Minimum Input Edge Rate (V/t) Data Input Enable Input 50 mV/ns 20 mV/ns -40C to +85C +4.5V to +5.5V
Note 4: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 5: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH VOL IIH IBVI IIL VID IIH + IOZH IIL + IOZL IOS ICEX IZZ ICCH ICCL ICCZ ICCT ICCD Output Short-Circuit Current Output HIGH Leakage Current Bus Drainage Test Power Supply Current Power Supply Current Power Supply Current -100 -275 50 100 1.0 68 1.0 2.5 No Load 0.23 mA A A mA mA mA mA mA/ MHz Max Max 0.0 Max Max Max Max Max VOUT = 0V VOUT = VCC VOUT = 5.5V; All Others GND All Outputs HIGH An or Bn Outputs LOW OEn = VCC, All Others at VCC or GND Additional ICC/Input Dynamic ICC (Note 6)
Note 6: Guaranteed, but not tested.
Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input LOW Current Input Leakage Test Output Leakage Current
Min 2.0
Typ
Max
Units V
VCC
Conditions Recognized HIGH Signal Recognized LOW Signal
0.8 -1.2 2.5 2.0 0.55 1 1 7 -1 -1 4.75 10 -10
V V V V V A A A V A A Min Min Min Min Max Max Max 0.0
IIN = -18 mA IOH = -3 mA IOH = -32 mA IOL = 64 mA VIN = 2.7V (Note 6) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 6) VIN = 0.0V IID = 1.9 A All Other Pins Grounded
0 - 5.5V VOUT = 2.7V; OE, OE = 2.0V 0 - 5.5V VOUT = 0.5V; OE, OE = 2.0V
Output Leakage Current
VI = VCC - 2.1V All Others at VCC or GND Outputs Open Transparent Mode One Bit Toggling, 50% Duty Cycle
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74ABT16501
DC Electrical Characteristics
Symbol VOLP VOLV VOHV VIHD VILD Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL Minimum HIGH Level Dynamic Output Voltage Minimum HIGH Level Dynamic Input Voltage Maximum LOW Level Dynamic Input Voltage -1.5 2.5 2.2 Min Typ 0.7 -1.0 3.0 1.8 1.2 0.8 Max 1.2 Units V V V V V VCC 5.0 5.0 5.0 5.0 5.0 Conditions CL = 50 pF; RL = 500 TA = 25C (Note 7) TA = 25C (Note 7) TA = 25C (Note 8) TA = 25C (Note 9) TA = 25C (Note 9)
Note 7: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 8: Max number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. Note 9: Max number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD ). Guaranteed, but not tested.
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fmax tPLH tPHL tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay A or B to B or A Propagation Delay LEAB or LEBA to B or A Propagation Delay CLKAB or CLKBA to B or A Propagation Delay OEAB or OEBA to B or A Propagation Delay OEAB or OEBA to B or A 150 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 VCC = +5V CL = 50 pF Typ 200 2.7 3.2 3.1 3.6 3.4 3.7 2.7 3.0 3.7 3.2 4.6 4.6 5.0 5.5 5.3 5.3 5.6 5.6 6.0 6.0 Max TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Min 150 1.0 1.0 1.0 1.0 1.0 1.0 1.5 1.5 1.5 1.5 4.6 4.6 5.0 5.5 5.3 5.3 5.6 5.6 6.0 6.0 ns ns ns ns Max MHz ns Units
AC Operating Requirements
TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) ts(L) tH(H) tH(L) tW(H) tW(L) tW(H) tW(L) Setup Time, A to CLKAB, B to CLKBA Hold Time, A to CLKAB, B to CLKBA Setup Time, A to LEAB or B to LEBA, CLK HIGH Hold Time, A to LEAB or B to LEBA, CLK HIGH Setup Time, A to LEAB or B to LEBA, CLK LOW Hold Time, A to LEAB or B to LEBA, CLK LOW Pulse Width, LEAB or LEBA, HIGH Pulse Width, CLKAB or CLKBA, HIGH or LOW 4.0 4.0 0 0 4.0 4.0 1.5 1.5 1.5 1.5 1.5 1.5 3.3 3.3 3.3 3.3 VCC = +5V CL = 50 pF Max Min 4.0 4.0 0 0 4.0 4.0 1.5 1.5 1.5 1.5 1.5 1.5 3.3 3.3 3.3 3.3 ns ns ns ns ns ns ns TA = -40C to +85C VCC = 4.5V-5.5V CL = 50 pF Max ns Units
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74ABT16501
Capacitance
Symbol CIN CI/O (Note 10) Parameter Input Capacitance Output Capacitance Typ 5.0 11.0 Units pF pF VCC = 0.0V VCC = 5.0V Conditions TA = 25C
Note 10: CI/O is measured at frequency f = 1 MHz per MIL-STD-883, Method 3012.
AC Loading
*Includes jig and probe capacitance.
FIGURE 1. Standard AC Test Load Input Pulse Requirements Amplitude 3.0V Rep. Rate 1 MHz tW 500 ns tr 2.5 ns
FIGURE 2. VM = 1.5V
tf 2.5 ns
FIGURE 3. Test Input Signal Requirements
AC Waveforms
FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions
FIGURE 6. 3-STATE Output HIGH and LOW Enable and Disable Times
FIGURE 5. Propagation Delay, Pulse Width Waveforms
FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms
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74ABT16501
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS56A
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74ABT16501 18-Bit Universal Bus Transceivers with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD56
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or systems device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the sonably expected to cause the failure of the life support body, or (b) support or sustain life, and (c) whose failure device or system, or to affect its safety or effectiveness. to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the www.fairchildsemi.com user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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